After the recovery instant, the parasitic inductance in the current path results in a voltage swing to try to maintain the current in the path. This results in a recovery current that flows through Q1 and the body diode of Q2, which represents a shoot-through scenario until the body diode of Q2 is completely recovered. Recovery losses together with this recovery current, in combination with the circuit’s parasitic elements can result in a voltage spikes (Figure 2).ĭuring stage five of a full-bridge conversion, the body diode of Q2 is reverse biased while it is still conducting current. The turn on speed of the high side FET, sets the di/dt of this recovery current. This results in stored charge (Qrr) which is removed in the form a momentary shoot-through when the high side FET turns on. in synchronous rectification applications (Figure 1) and during the continuous conduction mode of operation, the effects of Qrr are evident.ĭuring dead time, both high side and low side FETs are turned off allowing the low side body diode to conduct the freewheeling current. When the body diode of the MOSFET is allowed to conduct, e.g. Table 1: Losses in real-life applications However, it is worth noting that this power is dissipated in the gate drive components (external Rg and gate driver) so appropriate thermal provisions need to be made (Table 1). In practical terms, even a considerable Qg difference can have a minimal or even no effect on most applications.
That makes them effectively negligible for most applications. The gate driving capacity of today’s controllers has increased significantly, however and in more complex topologies a simple external gate drive stage can easily provide sufficient source and sink currents to drive several hundreds of nC under most practical conditions.Įven in terms of power efficiency, from an overall system perspective the losses when charging and discharging a gate are usually only a small fraction of the system power rating. In older systems, the gate driving capacity of controllers was a limiting factor, especially in applications where the MOSFETs are paralleled. Adjusting Rg during the design-in stage has a great impact in achieving the required switching performance. This is why almost every application uses an external gate resistor (Rg) to control dv/dt and its associated effects. A 50nC MOSFET switching a 48V line and a 5.0A drive can be turned off in 10ns, but it will result in an enormous 48,000V/µs of dv/dt. A MOSFET with a lower Qg can therefore be turned on and off quicker for any given gate drive current, potentially reducing switching losses.įigure 1: Qrr and shoot through in synchronous buck topology For example, theoretically a MOSFET with 50nC being driven by a 1.0A source and sink current, can be turned on in 50ns and turned off in another 50ns. Qg in its purest sense, helps define the switching times at any given gate drive current and gives a practical comparison of switching performance between MOSFETs. Redefining the MOSFET’s FoM would allow the choice of the right MOSFETs to improve efficiency but also bearing in mind voltage spiking and the design’s EMI signature. We therefore need to elaborate on how important Qrr is and how Qg is becoming less critical. The traditional FoM definition often acts as a gating factor for MOSFET selection, for today’s motor drive and switch mode power supply (SMPS) topologies. In pursuing the traditional FOM some manufacturers are spending resources to further optimise an already good Qg at the potential expense of other critical parameters. It was a good indicator at the time of its definition, but most modern MOSFETs now have an optimised Qg. From a conduction and switching performance perspective we are all accustomed to looking at the FoM for MOSFETs as a product of the drain-source on resistance RDS(on) and the gate charge Qg (FOM = RDS(on) x Qg).
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